It is known that, in a logic circuit such as an IC device circuit using CMOS gates or other types of gates, the amount of heat dissipation will change with the change of the number of pulses applied thereto, i.e., a frequency of an input pulse signal. This is because, in such an IC device circuit, current flows only at the signal transition edges, i.e., rising (leading) and falling (trailing) edges. Thus, the number of pulses or frequency of the input pulse signal is large, the number of occasions for current flowing in the CMOS circuit increases, resulting in the increase in the heat dissipation and the rise of the temperature in the CMOS circuit. The present invention is directed to a power consumption control circuit which regulates the CMOS logic circuit in such a way to maintain the amount of overall current (power consumption or heat dissipation) constant even though the number of pulses propagating through the CMOS logic circuit vary.
More detailed description regarding the heat dissipation by a CMOS circuit is provided in the following with reference to FIGS. 4 and 5. FIG. 4A shows an example of CMOS component such as an inverter circuit formed by CMOS transistors. A transistor MP is a P-channel MOS transistor and a transistor NP is an N-channel MOS transistor, which are connected complimentarily with each other. An input terminal 1 is commonly connected to gates of both of the transistors MP and NP, and an output terminal 2 is provided at a connection point of the transistors MP and NP. An example of FIG. 4B shows two pairs of transistors MP and NP to achieve a larger capacity of output current to increase a fanout (a number of output lines that can be fed by the output terminal).
In FIGS. 4A and 4B, VDD designates a high supply voltage (high voltage H) such as 4 V while VSS designates a low supply voltage (low voltage L) such as 0 V or ground. When the low voltage L is provided to the input terminal 1, the transistor MP is on (conductive) and the transistor NP is off (nonconductive), resulting in an output voltage of high voltage H at the output terminal. Conversely, when the high voltage H is provided to the input terminal 1, the transistor MP is off (nonconductive) and the transistor NP is on (conductive), resulting in an output voltage of low voltage L at the output terminal.
In the CMOS logic circuit such as shown in FIG. 4, in response to signal transition edges, i.e., rising and falling edges of an input pulse signal P of FIG. 5A, both transistors MP and NP become temporarily active. Thus, as shown in FIG. 5B, current flows during these transition periods. The amount of current during this period ranges from several ten micro amperes (.mu.A) to several milliamperes (mA). The current flow during this period affects a signal propagation delay time in the CMOS circuit as well as the amount of supply voltages. Other than the transition period noted above, only one of the transistors MP and NP is active in which the amount of current flowing in the active transistor is very small.
FIG. 6A shows an example in which a CMOS circuit is affected by such changes in the supply voltages. In this example, a large number of CMOS components such as inverters or buffers are aligned like a manner of matrix on an IC substrate. Main voltage lines are also provided on the substrate to surround the matrix of the CMOS components for providing supply voltages VDD and VSS. A number of fine lines are running from the main voltage lines to the CMOS components. Thus, each of the CMOS components is provided with supply voltages through fine voltage lines connected to the main voltage lines.
FIG. 6B shows an equivalent circuit of the CMOS circuit of FIG. 6A in which reference R designates resistance in each of the fine voltage lines connected to the CMOS components 10. Because the combinations of resistance R vary depending on the physical locations CMOS components 10 or numbers of CMOS components 10 driven at that time, actual amounts of supply voltages to the CMOS components 10 vary by the voltage drops across the resistance R. For example, the voltage V of the source voltage VDD at a specific CMOS component can be V=4.0-2iR or V=4.0-8iR, where i is a current flowing through the fine voltage line.
In the following, it is considered the relationship between the signal propagation delay time in a CMOS circuit 11 and inner current waveforms (power consumption) in the CMOS circuit 11 with reference to FIG. 7. In the example of FIG. 7 and within the context of this specification, the CMOS circuit 11 is a circuit having a large number of CMOS components, such as several ten to a hundred CMOS inverters, buffers or gates or the like, connected in series.
In FIG. 7, a pulse signal P propagates through the CMOS circuit 11 having a large number of CMOS components 10 therein. The pulse signal at an input terminal 3 is designated by an input pulse PI and the pulse signal at an output terminal 4 is designated by an output pulse PO. FIG. 8 is a timing chart showing the waveforms associated with the example of FIG. 7. The input pulse PI shown in FIG. 8A at the input terminal 3 propagates through the CMOS circuit 11 and the output pulse PO comes out at the output terminal 4 after a signal propagation delay time Td of the CMOS circuit 11 as shown in FIG. 8B.
Typically, a signal propagation delay time of each CMOS component is about 10 ps (picosecond), although it varies depending on the supply voltage, the number of stages or temperature. Since the large number of CMOS components, such as several ten to a hundred, are connected in series, an overall propagation delay time between the input terminal 3 and the output terminal 4 of the CMOS circuit 11 may amount to several nanoseconds.
The current waveforms in the CMOS circuit 11 are shown in FIG. 8C. Each of the current waveforms in FIG. 8C is considered with respect to time periods 1, 2 and 3 of FIG. 8D. The current waveform in the time period 1 represents a current i flowing in the CMOS circuit 11 caused by the rising (leading) edge of the pulse signal. The current waveform in the time period 2 represents a current 2i flowing in the CMOS circuit 11 caused by both the rising (leading) edge and the falling (trailing) edge of the pulse signal. The current waveform in the time period 3 represents a current i flowing in the CMOS circuit 11 caused by the falling (trailing) edge of the pulse signal.
As can be seen in FIG. 8C, an overall current flowing in the CMOS circuit, i.e., power consumption therein, depends on whether a pulse signal is applied to the circuit, and the repetition rate (frequency) of the pulse signal. Therefore, the temperature of the CMOS circuit varies depending on the pulse signal supplied thereto and its repetition rate. As noted above, the supply voltages to the CMOS components also vary depending on the voltage drops across the resistance in the fine voltage lines.
In a CMOS circuit, it is known that the delay time Td for a pulse signal P to propagate therethrough is dependent upon the temperature and supply voltages of the CMOS components. The signal propagation delay time Td increases in a manner of second order curve with the increase of the temperature. Further, the signal propagation delay time Td increases in a manner of second order curve with the decrease of the supply voltage. Therefore, a built-in temperature compensation circuit is frequently used in a CMOS circuit which requires high timing resolution and accuracy such as a delay circuit. Typically, such a temperature compensation circuit in a delay circuit includes one or more dummy circuits or heaters.
One of the examples of such temperature compensation circuits is disclosed by an assignee of this invention in Japanese Patent Laid-Open Publication No. 8-330920 "Temperature Balance Circuit", a schematic structure of which is shown in FIG. 9. In the example of FIG. 9, a dummy CMOS circuit 12 is provided in close proximity to the CMOS circuit 11 to be compensated. The dummy CMOS circuit 12 has CMOS components whose number is substantially the same as that of the CMOS circuit 11. Basically, the dummy circuit 12 receives pulse signals in such a manner that an overall number of pulses propagating through both the CMOS circuit 11 and the dummy circuit 12 is constant.
FIG. 10 is a timing chart showing an operation of the temperature compensation circuit of FIG. 9. An input terminal 3 of the CMOS circuit 11 receives a pulse signal PI as shown in FIG. 10A and outputs an pulse PO at an output terminal 4 as shown in FIG. 10C. For a time cycle where the input pulse PI is absent, a pulse signal is provided at an input terminal 3n of the dummy circuit 12 as shown in FIG. 10B which is output at an output terminal 4n as shown in FIG. 10D. Thus, an overall number of pulses propagating through both the CMOS circuit 11 and the dummy circuit 12 is constant.
In other words, the overall number of pulses is set to the maximum, i.e., the highest possible frequency of the input pulse signal. If the number of input pulses to the CMOS circuit 11 is lower than the maximum rate, the difference is supplemented in the dummy CMOS circuit 12. Thus, the sum of currents flowing in the CMOS circuit 11 and the dummy circuit 12 is unchanged at all times as shown in FIG. 8E, resulting in the constant temperature (power consumption) even when the pulse repetition rate of the input pulse signal for the CMOS circuit 11 changes.
To make the overall number of pulses constant, in the conventional example of FIG. 9, a pulse counter and calculation means (not shown) interact to count the number of pulses supplied to the CMOS circuit 11 and to determine a difference between the counted number and the predetermined maximum number. Then the number of dummy pulses which satisfy the difference is input to the dummy CMOS circuit 12, resulting in the total number of pulses which is always equal to the maximum number.
This conventional temperature compensated logic circuit in the above is effective in regulating the temperature of the CMOS logic circuit unchanged without regard to the repetition rate of the pulse signal passing therethrough. However, this example has a disadvantage in that it requires the dummy circuit 12 having a number of components which is comparable to the CMOS logic circuit 11 to be compensated. Thus, an overall circuit size may be about two times as large as the CMOS circuit 11.
Moreover, since the input pulse PI propagating through the CMOS circuit and the pulse signal supplemented in the dummy circuit 12 are asynchronouse with one another, the voltage drops in the supply voltage lines of the CMOS components noted above vary with the types of input pulse signals supplied thereto or combinations of CMOS components receiving the input pulses. This uneven voltage drops in the supply voltages also cause fluctuations in the signal propagation delay time in the CMOS circuit.